PCF2123TS datasheet(9/55 Pages) NXP

9 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

9 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

9.3 Control registers

9.3.1 Register Control_1

[1]

Default value.

[2]

For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 9.5).

Table 5.

Control_1 - control and status register 1 (address 00h) bit description

Bit

Symbol

Value

Description

Reference

EXT_TEST

0[1]

normal mode

Section 9.12

external clock test mode

unused

5STOP

0[1]

the RTC source clock runs

Section 9.13

the RTC clock is stopped;

RTC divider chain ﬂip-ﬂops are

asynchronously set to logic 0;

CLKOUT at 32.768 kHz, 16.384 kHz or

8.192 kHz is still available

4SR

0[1]

no software reset

Section 9.5

initiate software reset[2];

this register will always return a 0 when

read

unused

12_24

0[1]

24 hour mode is selected

12 hour mode is selected

CIE

0[1]

no correction interrupt generated

Section 9.11

interrupt pulses will be generated at every

correction cycle

unused

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