PCF2123TS datasheet(7/55 Pages) NXP

7 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

7 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

9.1.2 Power consumptions with respect to timer mode

Four source clocks are possible for the timer. The 4.096 kHz source clock will add the

greatest part to the power consumption. The selection of 64 Hz, 1 Hz or 1

⁄

60 Hz will be

almost indistinguishable and add very little.

Conﬁguration: CLKOUT disabled, VDD = 3 V, timer clock set to 1⁄60 Hz.

(1) IDD (nA) minimum power mode.

(2) Maximum value for RS is 100 kΩ.

Fig 6.

IDD with respect to quartz RS

Rs(2) (k

Ω)

100

001aai558

130

170

210

250

IDD(1)

(nA)

Conﬁguration: CLKOUT disabled, quartz RS =15kΩ.

(1) IDD (nA) minimum power mode.

(2) Timer clock = 4 kHz.

(3) Timer clock = 64 Hz, 1 Hz, 1

⁄60 Hz.

Fig 7.

IDD with respect to timer clock selection

VDD (V)

001aai559

200

100

300

400

IDD(1)

(nA)

(2)

(3)

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