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68HC05CL16 Datasheet(PDF) 72 Page - Motorola, Inc |
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68HC05CL16 Datasheet(HTML) 72 Page - Motorola, Inc |
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72 / 145 page  GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA TIMER MC68HC05CL48 8-20 REV 2.0 Figure 8-7. ONE Second Watch Timer 8.3.1 Watch Timer Control & Status Register (WTCSR) WTOFF 1 = Disable Watch Timer 0 = Enable Watch Timer WTR Writing a ‘1’ to this bit will generate a reset pulse to reset the Watch Timer. Reading this bit will always return a ‘0’. WTOIE 1 = Enable 1 second interrupt. 0 = Disable 1 second interrupt. WTOF 1 = Flag set by transition of the 15-bit free running counter from $7FFF to $0000 0 = Flag cleared by writing a 0 to the WTOF bit. 7654 3 210 WTCSR $0023 READ WTOFF 0 WTOIE WTOF WRITE WTR RESET ---- 0 0 0 0 U = UNAFFECTED 15-bit Free Running Counter 32kHz External Clock WTOIE WRT WTOFF WTOF RESET OFF 1 second overflow WTimer Interrupt |
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