68HC05CL16 datasheet(89/145 Pages) MOTOROLA

89 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

CALLER-ID

MOTOROLA

REV 2.0

11-5

Figure 11-6. Power Up Sequence from WAIT Mode

11.6

DATA INTERFACE

The demodulated data from this module is available in bit-serial and 8-bit format.

The serial data can be read from CIDSD (bit 2) of the CLCSR2 register and the 8-

bit data is available from the Caller_ID data register CDDR. This data includes the

alternate 0 and 1 pattern, 150 ms marking which precedes data. At all other times

the demodulator output bit is high.

The Caller_ID data ready ﬂag CDRF bit-2 of CLCSR3 will be set to indicate that

the 8-bit data is ready to be read. The data ready ﬂag will generate an CPU

interrupt if the data ready interrupt enable DRIE bit-3 of CLCSR3 is set and the I-

bit of the CCR is cleared. The Caller_ID data register CDDR acts as data buffer for

the serial to parallel data conversion register and should be read by the CPU

within 8.3msec after receiving the interrupt. Failure to do so will result data lost.

Reading the Caller_ID data register CDDR clears the Caller_ID data ready ﬂag.

Figure 11-9 shows the timing diagram for the serial to parallel data conversion.

CPU WAIT MODE

CDPW?

POWER ON

CDIE?

CD INTERRUPT

YES

WAKE UP CPU

CARRIER DETECT

68HC05CL16 Datasheet(PDF) 89 Page - Motorola, Inc