AT90PWM2 datasheet(95/361 Pages) ATMEL

95 / 361 page

4317J–AVR–08/10

AT90PWM2/3/2B/3B

Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f

clk_I/O/8)

Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f

clk_I/O/8)

14.8

8-bit Timer/Counter Register Description

14.8.1

Timer/Counter Control Register A – TCCR0A

TOVn

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

clk

I/O

clk

(clk

I/O/8)

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

210

COM0A1

COM0A0

COM0B1

COM0B0

–

WGM01

WGM00

TCCR0A

Read/Write

R/W

Initial Value

AT90PWM2 Datasheet(PDF) 95 Page - ATMEL Corporation

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