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AT90PWM2 Datasheet(PDF) 49 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 361 page  49 4317J–AVR–08/10 AT90PWM2/3/2B/3B Figure 9-5. Brown-out Reset During Operation 9.0.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Refer to page 50 for details on operation of the Watchdog Timer. Figure 9-6. Watchdog Reset During Operation 9.0.7 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag VCC RESET TIME-OUT INTERNAL RESET VBOT- VBOT+ tTOUT CK CC Bit 7 65 43 21 0 – – – – WDRF BORF EXTRF PORF MCUSR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description |
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