AT90PWM2 datasheet(34/361 Pages) ATMEL

34 / 361 page

4317J–AVR–08/10

AT90PWM2/3/2B/3B

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the fre-

quency range 7.3 - 8.1 MHz.

7.6

PLL

To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency

clock input. This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of

PLL must be configurable by software. With a system clock of 8 MHz, the PLL output is 32Mhz

or 64Mhz.

7.6.1

Internal PLL for PSC

The internal PLL in AT90PWM2/2B/3/3B generates a clock frequency that is 64x multiplied from

nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC

Oscillator which is divided down to 1 MHz. See the Figure 7-4 on page 35.

The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register

will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC

Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency satu-

rates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be

noted that the PLL in this case is not locked any more with the RC Oscillator clock.

Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1

MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only

when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is

set when PLL is locked.

Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep

modes

Table 7-9.

Start-up Times when the PLL is selected as system clock

CKSEL

3..0

SUT1..0

Start-up Time from Power-down

and Power-save

Additional Delay from Reset

CC = 5.0V)

0011

RC Osc

1K CK

14CK

1K CK

14CK + 4 ms

1K CK

14CK + 64 ms

16K CK

14CK

AT90PWM2 Datasheet(PDF) 34 Page - ATMEL Corporation

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