MPC8315ECVRAGDA datasheet(21/112 Pages) FREESCALE

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MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 18 and Table 19 lists the input AC timing specifications for the DDR SDRAM interface.

Figure 6 shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (tDISKEW)

Figure 6. Timing Diagram for tDISKEW

Table 18. DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 V± 100 mV)

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ

266 MHz

200 MHz

tCISKEW

–875

–1250

875

1250

1, 2, 3

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to be

captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

3. Memory controller ODT value of 150

Ω is recommended.

Table 19. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of (2.5V ± 200 mV)

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ

266 MHz

200 MHz

tCISKEW

–750

–1250

750

1250

1, 2

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to be

captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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