MPC8315ECVRAGDA datasheet(67/112 Pages) FREESCALE

67 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

PCI Express

Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications

16.4.3

Differential Receiver (RX) Input Specifications

Table 55 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 55. Differential Receiver (RX) Input Specifications

Parameter

Symbol

Comments

Min

Typical

Max

Units

Notes

Unit interval

Each UI is 400 ps ± 300 ppm.

UI does not account for

Spread Spectrum Clock

dictated variations.

399.88

400

400.12

Differential peak-to-peak

output voltage

VRX-DIFFp-p

VRX-DIFFp-p = 2*|VRX-D+ -

VRX-D-|

0.175

—

1.200

Minimum receiver eye

width

TRX-EYE

The maximum interconnect

media and Transmitter jitter

that can be tolerated by the

Receiver can be derived as

TRX-MAX-JITTER = 1 -

URX-EYE= 0.6 UI.

0.4

——UI

2, 3

[De-emphasized Bit]

566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

MPC8315ECVRAGDA Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc

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