MPC8315ECVRAGDA datasheet(97/112 Pages) FREESCALE

97 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Clocking

The primary clock source can be one of two inputs, SYS_CLKIN or PCI_CLK, depending on whether the

device is configured in PCI host or PCI agent mode. When the device is configured as a PCI host device,

SYS_CLKIN is its primary input clock. SYS_CLKIN feeds the PCI clock divider (

÷2) and the

multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_SYS_CLKIN_DIV configuration

input selects whether SYS_CLKIN or SYS_CLKIN/2 is driven out on the PCI_SYNC_OUT signal.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to

synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,

with equal delay to all PCI agent devices in the system, to allow the device to function. When the device

is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured

as a PCI agent device the SYS_CLKIN signal should be tied to GND.

As shown in Figure 62, the primary clock input (frequency) is multiplied up by the system phase-locked

loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the

DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following

equation:

csb_clk = {PCI_SYNC_IN × (1 + ~ CFG_SYS_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + ~ CFG_SYS_CLKIN_DIV) is the SYS_CLKIN frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up

the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL

multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)

which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,

Clocking, and Initialization,” in the MPC8315E PowerQUICC II Pro Host Processor Reference Manual

for more information on the clock subsystem.

The internal ddr_clk frequency is determined by the following equation:

ddr_clk = csb_clk × (1 + RCWL[DDRCM])

Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider

(

÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate

is the same frequency as ddr_clk.

The internal lbiu_clk frequency is determined by the following equation:

lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])

Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider

to create the external local bus clock outputs (LCLK[0:1]). The LBIU clock divider ratio is controlled by

LCCR[CLKDIV].

In addition, some of the internal units may be required to be shut off or operate at lower frequency than

the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped

frequency.

MPC8315ECVRAGDA Datasheet(PDF) 97 Page - Freescale Semiconductor, Inc