MPC8315ECVRAGDA datasheet(79/112 Pages) FREESCALE

79 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

TDM

Figure 51 shows the TDM receive signal timing.

Figure 59. TDM Receive Signals

TDMxTFS/TDMxRFS input hold time

tDMFSIXKH

2.0

—

TDMxTCK High to TDMxTD output active

tDM_OUTAC

4.0

—

TDMxTCK High to TDMxTD output valid

tDMTKHOV

—

14.0

TDMxTD hold time

tDMTKHOX

2.0

—

TDMxTCK High to TDMxTD output high impedance

tDM_OUTHI

—

10.0

TDMxTFS/TDMxRFS output valid

tDMFSKHOV

—

13.5

TDMxTFS/TDMxRFS output hold time

tDMFSKHOX

2.5

—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTDMIVKH symbolizes TDM

timing (DM) with respect to the time the input signals (I) reach the valid state (V) relative to the TDM Clock, tTC, reference (K)

going to the high (H) state or setup time. Also, output signals (O), hold (X).

2. Output values are based on 30 pF capacitive load.

3. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge

they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and TDMxRCK

are shown using the rising edge.

Table 69. TDM AC Timing specifications

Parameter/Condition

Symbol

Min

Max

Units

TDMxRCK

TDMxRD

TDMxRFS

TDMxRFS (output)

tDM

tDM_HIGH

tDM_LOW

tDMIVKH

tDMRDIXKH

tDMFSIXKH

tDMFSKHOV

tDMFSKHOX

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