IMX53CEC datasheet(85/204 Pages) FREESCALE

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Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

4.7.8.2

Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.7.8.2.1

BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing

syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data

stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking

is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data

stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one

component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are

received over the SENSB_DATA bus.

4.7.8.2.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 44.

Figure 44. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the

corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid

as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

2 The MSB bits are duplicated on LSB bits implementing color extension

3 The two MSB bits are duplicated on LSB bits implementing color extension

4 RGB 16 bits – supported in two ways: (1) As a “generic data” input – with no on-the-fly processing; (2) With on-the-fly

processing, but only under some restrictions on the control protocol.

5 YCbCr 16 bits - supported as a “generic-data” input – with no on-the-fly processing.

6 YCbCr 16 bits - supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).

7 YCbCr, 20 bits, supported only within the BT.1120 protocol (syncs embedded within the data stream).

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Active Line

Start of Frame

IMX53CEC Datasheet(PDF) 85 Page - Freescale Semiconductor, Inc

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