STM32F050C4 datasheet(82/97 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F050xx

82/97

Doc ID 023683 Rev 1

Table 60.

I2S characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fCK

1/tc(CK)

I2S clock frequency

Master mode (data: 16 bits, Audio

frequency = 48 kHz)

1.597

1.601

MHz

Slave mode

6.5

tr(CK)

I2S clock rise time

Capacitive load CL =15 pF

-10

tf(CK)

I2S clock fall time

tw(CKH)

(1)

I2S clock high time

Master fPCLK= 16 MHz, audio

frequency = 48 kHz

306

tw(CKL)

(1)

I2S clock low time

312

tv(WS)

(1)

WS valid time

Master mode

th(WS)

(1)

WS hold time

Master mode

tsu(WS)

(1)

WS setup time

Slave mode

th(WS)

(1)

WS hold time

Slave mode

DuCy(SCK)

I2S slave input clock duty

cycle

Slave mode

tsu(SD_MR)

(1)

Data input setup time

Master receiver

tsu(SD_SR)

(1)

Data input setup time

Slave receiver

th(SD_MR)

(1)(2)

Data input hold time

Master receiver

th(SD_SR)

(1)(2)

Slave receiver

0.5

tv(SD_ST)

(1)(2)

Data output valid time

Slave transmitter (after enable

edge)

-20

th(SD_ST)

(1)

Data output hold time

Slave transmitter (after enable

edge)

tv(SD_MT)

(1)(2)

Data output valid time

Master transmitter (after enable

edge)

th(SD_MT)

(1)

Data output hold time

Master transmitter (after enable

edge)

Data based on design simulation and/or characterization results, not tested in production.

Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.

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