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STLUX385ATR Datasheet(PDF) 57 Page - STMicroelectronics |
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STLUX385ATR Datasheet(HTML) 57 Page - STMicroelectronics |
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57 / 99 page ![]() DocID024387 Rev 2 57/98 STLUX385A Option bytes nUBC (UBC user boot code reg. protection) nUBC: not(UBC) EMC byte protection. GENCFG (general configuration reg.) Bit 0: EN_COLD_CFG enables IC cold configuration through the option byte register AFR_IOMXP0,P1: 0: default case, the IC multifunction signal configuration is performed by the miscellaneous registers MSC_IOMXP0 and MSC_IOMXP1 (warm configuration). 1: enables the multifunction signal configuration through the option byte registers AFR_IOMXP0 and AFR_IOMXP1 (cold configuration). Bit 1: COMP1_2 enables the complete backward compatibility with the previous device implementations. In detail, below features are inhibited: Multiplexing of I 2 C interface on GPIO[5:4], GPIO[1:0], DIGIN[5:4] Multiplexing of UART interface on GPIO[5:4] Port0 and Port2 interrupt mask feature (polling) DIGIN[5:0] pull-up disabling feature DALI noise rejection filter Note: This bit setting ensures the full device compatibility with the previous device model (STLUX385). Offset: 0x004802 Default value: 0xFF 7 6543 210 nUBC [7:0] r/w Offset: 0x004803 Default value: 0xFF 7 65432 1 0 Rst_PWM [5:0] COMP1_2 EN_COLD_C FG r/w r/w r/w |
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