STLUX385ATR datasheet(36/99 Pages) STMICROELECTRONICS

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I/O multifunction signal configuration

STLUX385A

36/98

DocID024387 Rev 2

MSC_IOMXP2 (Port P2 I/O mux control register)

Port1 I/O multifunction signal configurations register (for functionality description refers to

Section 5.4).

Bit 3-0:

RFU reserved; must be kept 0 during register writing for future compatibility

Bit 4:

Sel_p254 Port2[5:4] I/O multiplexing scheme:

0: Port2[5:4] are interconnected to I

C_scl and I

C_sda signals

1: Port2[5:4] are interconnected to DIGIN[5:4] signals

Bit 7-5:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0

during register write operations

MSC_INPP2AUX1 (INPP aux register)

Bit 5-0:

INPP2_PULCTR[5:0] This register configures respectively the INPP2[5:0] pull-up

functionality as follows:

0: Enable pad pull-up features (enabled by default for compatibility with the

STLUX385)

1: Disable pad pull-up

Bit 7-6:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0

during register write operations.

Note:

MSC_IOMXP2 and MSC_INPP2AUX1 are addressable in indirect mode.

Offset: 0x13 (indirect area)

Default value: 0xFF

6543

210

RFU

Sel_p254

RFU

r/w

Offset: 0x08

Default value: 0x00

6543

210

RFU

INPP2_PULCTR [5:0]

rr/w

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