MC9S08SH4MPJR datasheet(67/341 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08SH8 MCU Series Data Sheet, Rev. 3

Freescale Semiconductor

The status ﬂag corresponding to the interrupt source must be acknowledged (cleared) before returning

from the ISR. Typically, the ﬂag is cleared at the beginning of the ISR so that if another interrupt is

generated by this same source, it will be registered so it can be serviced after completion of the current ISR.

5.5.2

External Interrupt Request Pin (IRQ)

External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is

enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in

stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)

can wake the MCU.

5.5.2.1

Pin Configuration Option

The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt

request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected

(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event

causes an interrupt or only sets the IRQF ﬂag which can be polled by software.

The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-up

or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down,

the IRQPDD can be written to a 1 to turn off the internal device.

BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is conﬁgured to act

as the IRQ input.

NOTE

This pin does not contain a clamp diode to VDD and should not be driven

above VDD.

The voltage measured on the internally pulled up IRQ pin will not be pulled

to VDD. The internal gates connected to this pin are pulled to VDD. If the

IRQ pin is required to drive to a VDD level an external pullup should be used.

5.5.2.2

Edge and Level Sensitivity

The IRQMOD control bit reconﬁgures the detection logic so it detects edge events and pin levels. In the

edge and level detection mode, the IRQF status ﬂag becomes set when an edge is detected (when the IRQ

pin changes from the deasserted to the asserted level), but the ﬂag is continuously set (and cannot be

cleared) as long as the IRQ pin remains at the asserted level.

5.5.3

Interrupt Vectors, Sources, and Local Masks

Table 5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the

bottom of the table. The high-order byte of the address for the interrupt service routine is located at the

ﬁrst address in the vector address column, and the low-order byte of the address for the interrupt service

routine is located at the next higher address.

MC9S08SH4MPJR Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc