ADE7759_15 datasheet(15/36 Pages) AD

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REV. A

ADE7759

–15–

INTERRUPTS

ADE7759 interrupts are managed through the interrupt status

(IRQEN[7:0]). When an interrupt event occurs in the ADE7759,

the corresponding flag in the status register is set to a Logic 1—see

Interrupt Status Register section. If the enable bit for this

interrupt in the interrupt enable register is Logic 1, then the

IRQ logic output goes active low. The flag bits in the status

To determine the source of the interrupt, the system master

(MCU) should perform a read from the status register with

reset (RSTATUS[7:0]). This is achieved by carrying out a

read from address 05h. The

IRQ output will go logic high on

completion of the interrupt status register read command—

see Interrupt Timing section. When carrying out a read with

reset, the ADE7759 is designed to ensure that no interrupt

events are missed. If an interrupt event occurs just as the status

IRQ

logic output is guaranteed to go high for the duration of the

interrupt status register data transfer before going logic low

again to indicate the pending interrupt. See the following

section for a more detailed description.

Using the ADE7759 Interrupts with an MCU

Figure 17 shows a timing diagram with a suggested implementa-

tion of ADE7759 interrupt management using an MCU. At

time t1, the IRQ line will go active low, indicating that one or

more interrupt events have occurred in the ADE7759. The

IRQ

logic output should be tied to a negative edge-triggered external

interrupt on the MCU. On detection of the negative edge, the

MCU should be configured to start executing its Interrupt Ser-

vice Routine (ISR). On entering the ISR, all interrupts should

be disabled using the global interrupt enable bit. At this point,

the MCU external interrupt flag can be cleared to capture inter-

rupt events that occur during the current ISR.

When the MCU interrupt flag is cleared, a read from the status

IRQ line to

be reset logic high (t2)—see Interrupt Timing section. The

status register contents are used to determine the source of

the interrupt(s), and thus the appropriate action will be taken. If

a subsequent interrupt event occurs during the ISR, that event

will be recorded by the MCU external interrupt flag being set

again (t3). On returning from the ISR, the global interrupt mask

will be cleared (same instruction cycle) and the external inter-

rupt flag will cause the MCU to jump to its ISR once again. This

will ensure that the MCU does not miss any external interrupts.

Interrupt Timing

The Serial Interface section should be reviewed first, before the

Interrupt Timing section. As previously described, when the

IRQ output goes low, the MCU ISR must read the interrupt

status register to determine the source of the interrupt. When

reading the status register contents, the

IRQ output is set high

on the last falling edge of SCLK of the first byte transfer (read

interrupt status register command). The

IRQ output is held

high until the last bit of the next 8-bit transfer is shifted out

(interrupt status register contents)—see Figure 18. If an inter-

rupt is pending at this time, the

IRQ output will go low again. If

no interrupt is pending, the

IRQ output will stay high.

IRQ

GLOBAL

INTERRUPT

MASK SET

CLEAR MCU

INTERRUPT

FLAG

READ

STATUS WITH

RESET (05h)

ISR ACTION

(BASED ON

STATUS CONTENTS)

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

MCU

INTERRUPT

FLAG SET

JUMP

ISR

MCU

PROGRAM

SEQUENCE

JUMP

ISR

Figure 17. Interrupt Management

SCLK

DIN

DOUT

IRQ

t11

READ STATUS REGISTER COMMAND

STATUS REGISTER CONTENTS

DB7

DB0

Figure 18. Interrupt Timing

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