ADE7759_15 datasheet(28/36 Pages) AD

28 / 36 page

REV. A

ADE7759

–28–

Table IV. Register List

Address

Name

R/W

No. of Bits Default

Description

01h

WAVEFORM

24/40

The Waveform Register is a read-only register. This register con-

tains the sampled waveform data from Channel 1, Channel 2, or the

active power signal. The data source and the length of the waveform

registers are selected by data bits 14 and 13 in the mode register—

see Channel 1 and 2 Sampling section.

02h

AENERGY

Active Energy Register. Active power is accumulated (Integrated)

over time in this 40-bit, read-only register. The energy register

can hold a minimum of 11.53 seconds of active energy information

with full-scale analog inputs before it overflows—see Energy Calcu-

lation section.

03h

RSTENERGY

Same as the active energy register except that the register is reset to

0 following a read operation.

04h

STATUS

40h

Interrupt Status Register. This is an 8-bit read-only register. The

status register contains information regarding the source of

ADE7759 interrupts—see Interrupts section.

05h

RSTSTATUS

Same as the interrupt status register except that the register con-

tents are reset to 0 (all flags cleared) after a read operation.

06h

MODE

R/W

000Ch

Mode Register. This is a 16-bit register through which most of

the ADE7759 functionality is accessed. Signal sample rates, filter

enabling, and calibration modes are selected by writing to this

section.

07h

CFDEN

R/W

3Fh

CF Frequency Divider Denominator Register. The output fre-

quency on the CF pin is adjusted by writing to this 12-bit read/write

08h

CH1OS

R/W

80h

Channel 1 Offset Adjust. The MSB is used to enable the digital inte-

grator. Bit 6 is not used. Writing to Bits 0 to 5 allows offsets on

Channel 1 to be removed—see Analog Inputs section and CH1OS

09h

CH2OS

R/W

Channel 2 Offset Adjust. Writing to this 6-bit register allows any offsets

on Channel 2 to be removed—see Analog Inputs section.

0Ah

GAIN

R/W

PGA Gain Adjust. This 8-bit register is used to adjust the gain selec-

tion for the PGA in Channel 1 and 2—see Analog Inputs section.

CHECKSUM REGISTER

The ADE7759 has a checksum register (CHKSUM[5:0]) to

ensure that the data bits received in the last serial read operation

are not corrupted. The 6-bit checksum register is reset before

the first bit (MSB of the register to be read) is put on the DOUT

pin. During a serial read operation, when each data bit becomes

available on the rising edge of SCLK, the bit will be added to

the checksum register. In the end of the serial read operation,

the content of the checksum register will be the sum of all the

ones contained in the register previously read. Using the checksum

the last read operation.

Note that a read to the CHKSUM register will also generate a

checksum of the CHKSUM register itself.

CONTENT OF REGISTER (n-bytes)

CHECKSUM REGISTER

ADDR: 1Eh

DOUT

Figure 47. Checksum Register for Serial Interface Read

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