AN2014 datasheet(26/65 Pages) STMICROELECTRONICS

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Hardware considerations

AN2014

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DocID10701 Rev 10

driven by a Master buffer configured as a push-pull (therefore the pull up resistor on SCL

line is not required).

For a safe design, the SCL line must never be left floating (Hi-Z) and must be driven low

when SDA transitions are not under control to avoid undesired START and STOP

conditions. As a consequence, Power up, Power down phases as well as Reset states, can

be secured using a pull-down resistor on the SCL line. This will minimize the chances of a

parasitic STOP/START condition, when the controller releases the I2C bus.

Note:

A STOP condition can be decoded as the trigger of a Write cycle if this STOP condition

appears at the end of a data byte inside a transmitted Write command.

The input pin leakage is negligible (typically a few nA). Input schematic (including a

protection circuit) does not offer any open path to VSS or VCC. Therefore SCL level can be

set before the EEPROM power up and can remain high even after power down with no risk

of high leakage or EOS.

Figure 19. Serial clock input SCL

4.1.4

Write control (WC)

The Write Control (WC) input includes an internal pull-down resistor, in case the application

designer leaves it floating (See Figure 20). If no write protection is necessary, it should be

directly tied to the VSS. The best write protection is obtained by connecting the Write Control

input to a Master output and a pull-up resistor to VCC (see Figure 22), thus allowing a default

write protection also during the critical Power-up, Power Down and Application Reset

phase. Prior to issuing any Write instruction the WC pin should be driven Low and it should

be maintained Low after the STOP condition ending the Write command.

Input pin leakage current depends on input pin voltage. See Table 6.

Ai11725

SCL pad

ESD/EOS Protection

Glitch Filter

Schmitt trigger

AN2014 Datasheet(PDF) 26 Page - STMicroelectronics