SI5341_16 datasheet(24/53 Pages) SILABS

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Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Notes:

1. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each out-

put driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the

TIA/EIA-644 maximum. Refer to the Si5341/40 Family Reference Manual for more suggested output settings. Not all combina-

tions of voltage amplitude and common mode voltages settings are possible.

OUTxb

OUTx

Vpp_se

Vpp_ diff = 2* Vpp_se

Vcm

2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude meas-

ured.

3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25

MHz. Refer to application note, AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems,

guidance on crosstalk minimization.

Table 5.6. LVCMOS Clock Output Specifications

(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDO=1.8V ± 5%, 2.5V ± 5%, or 3.3V ± 5%, TA= -40 to 85°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Output Frequency

0.0001

—

250

MHz

Duty Cycle

fOUT < 100 MHz

—

100 MHz < fOUT < 250 MHz

—

Output-to-Output Skew

TSK

Outputs on same MultiSynth.

FOUT = 156.25 MHz

—

140

Output Voltage High1, 2, 3

VOH

VDDO = 3.3 V

OUTx_CMOS_DRV=1

IOH = -10 mA

VDDO x 0.85

—

OUTx_CMOS_DRV=2

IOH = -12 mA

—

OUTx_CMOS_DRV=3

IOH = -17 mA

—

VDDO = 2.5 V

OUTx_CMOS_DRV=1

IOH = -6 mA

VDDO x 0.85

—

OUTx_CMOS_DRV=2

IOH = -8 mA

—

OUTx_CMOS_DRV=3

IOH = -11 mA

—

VDDO = 1.8 V

OUTx_CMOS_DRV=2

IOH = -4 mA

VDDO x 0.85

—

OUTx_CMOS_DRV=3

IOH = -5 mA

—

Si5341/40 Rev D Data Sheet

Electrical Specifications

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