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Timing and AC Characteristics

BCM20705 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

Bluetooth Transceiver and Baseband Processor

November 13, 2014 • MCS20705-DS104-R

Page 54

Timing and AC Characteristics

In this section, use the numbers listed in the reference column to interpret the timing diagrams.

Startup Timing

There are two basic startup scenarios. In one scenario, the chip startup and firmware boot is held off while the

RST_N pin is asserted. In the second scenario, the chip startup and firmware boot is directly triggered by the

chip power-up. In this case, an internal power-on reset (POR) is held for a few ms, after which the chip

commences startup.

The global reset signal in the BCM20705 is a logical OR (actually a wired AND, since the signals are active low)

of the RST_N input and the internal POR signals. The last signal to be released determines the time at which

the chip is released from reset. The POR is typically asserted for 3 ms after VDDC crosses the 0.8V threshold,

but it may be as soon as 1.5 ms after this event.

After the chip is released from reset, both startup scenarios follow the same sequence, as follows:

For the BCM20705A1KWFBG parts: after approximately 120 μs, the CLK_REQ (GPIO_5) signal is asserted

(not available on BCM20705B0KWFBG parts).

The chip remains in sleep state for a minimum of 4.2 ms.

If present, the crystal (or TCXO) and LPO clocks must be oscillating by the end of the 4.2 ms period.

If a TCXO clock is not in the system, a crystal is assumed to be present at the XIN and XOUT pins. If an LPO

clock is not used, the firmware will detect the absence of a clock at the LPO_IN lead and use the internal LPO

clock instead.

The following two figures illustrate two startup timing scenarios.

Note:

The GPIO5 (CLK_REQ) waveform does not apply to the BCM20705B0KWFBG.

BCM20705 Datasheet(PDF) 55 Page - Cypress Semiconductor