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LIS3MDL Datasheet(PDF) 10 Page - STMicroelectronics |
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LIS3MDL Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 33 page ![]() Magnetic and electrical specifications LIS3MDL 10/33 DocID024204 Rev 4 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram Note: Measurement points are done at 0.2• Vdd_IO and 0.8• Vdd_IO, for both input and output ports. Table 6. SPI slave timing values Symbol Parameter Value (1) 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. Unit Min. Max. tc(SPC) SPI clock cycle 100 ns fc(SPC) SPI clock frequency 10 MHz tsu(CS) CS setup time 5 ns th(CS) CS hold time 20 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 50 th(SO) SDO output hold time 5 tdis(SO) SDO output disable time 50 SPC CS SDI SDO tsu(CS) tv(SO) th(SO) th(SI) tsu(SI) th(CS) tdis(SO) tc(SPC) MSB IN MSB OUT LSB OUT LSB IN |
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