TNETV1647GSTZWT datasheet(143/236 Pages) TI1

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EM_CS[5:2]

Asserted

Deasserted

EM_BA[1:0]

EM_A[21:0]

EM_D[15:0]

EM_WE

EM_WAIT

SETUP

STROBE

Extended Due to EM_WAIT

STROBE

HOLD

TMS320DM6441

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SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

Figure 6-24. EM_WAIT Write Timing Requirements

6.10.2 DDR2 Memory Controller

The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A

standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM

devices. For details on the DDR2 Memory Controller, see the TMS320DM644x DMSoC Peripherals

Overview Reference Guide (literature number SPRUE19) and the TMS320DM644x DMSoC DDR2

Memory Controller User's Guide (literature number SPRUE22).

DDR2 SDRAM plays a key role in a DM6441-based system. Such a system is expected to require a

significant amount of high-speed external memory for:

•

Buffering of input image data from sensors or video sources

•

Intermediate buffering for processing/resizing of image data in the VPFE

•

Numerous OSD display buffers

•

Intermediate buffering for large raw Bayer data image files while performing image processing

functions

•

Buffering for intermediate data while performing video encode and decode functions

•

Storage of executable code for both the ARM and DSP

A memory map of the DDR2 memory controller registers is shown in Table 6-36.

Peripheral and Electrical Specifications

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