TNETV1647GSTZWT datasheet(146/236 Pages) TI1

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TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

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6.11.2 ATA/CF Electrical Data/Timing

All ATA/CF AC timing data described in Table 6-39 – Figure 6-26 is provided at the DM6441 device

pins. For more details, see Section 6.1, Parameter Information.

The AC timing specifications described in Table 6-39 – Figure 6-26 assume correct configuration of

the ATA/CF memory-mapped control registers for the selected ATA/CF frequency of operation.

6.11.2.1 ATA/CF PIO Data Transfer AC Timing

Table 6-39. Timings for ATA/CF Module — PIO Data Transfer(1) (2) (see Figure 6-26)

1.05 V and 1.2 V

NO.

MODE

UNIT

MIN

MAX

Cycle time

0-4(3)

(DATSTB + DATRCVR + 2)P - 0.5

Address valid to DIOW/ DIOR setup

0-4(3)

12P - 1.6

DIOW/ DIOR pulse duration low

0-4(3)

(DATSTB + 1)P - 1

0-2

–

t2i

DIOW/DIOR recovery time, pulse duration high

3-4(3)

(DATRCVR + 1)P - 1

DIOW data setup time, DD[15:0] valid before

0-4(3)

(DATSTB + 1)P

DIOW rising edge

DIOW data hold time, DD[15:0] valid after DIOW

0-4(3)

(HWNHLD + 1)P + 1

rising edge

DIOR data setup time, DD[15:0] valid before DIOR

rising edge

2-4(3)

DIOR data hold time, DD[15:0] valid after DIOR

0-4(3)

rising edge

Output data 3-state, DD[15:0] 3-state after DIOR

t6Z

0-4(3)

rising edge

DIOW/DIOR to address valid hold

0-4(3)

(HWNHLD + 1)P - 2.1

Read data setup time, DD[15:0] valid before

tRD

0-4(3)

IORDY active

IORDY setup

0-4(3) (4)

IORDY pulse width

0-4(3)

1250

IORDY assertion to release

0-4(3)

(1)

P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 405 MHz, use P = 14.8 ns.

(2)

DATSTB equals the value programmed in the DATSTBxP bit field in the DATSTB register. DATRCVR equals the value programmed in

the DATRCVRxP bit field in the DATRCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the

MISCCTL register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number

SPRUE21).

(3)

The sustained throughput for PIO modes 3 and 4 is limited to the throughput equivalent of PIO mode 2. For more detailed information,

see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number SPRUE21).

(4)

The tA parameter must be met only when the IORDY timer is enabled to allow a device to insert wait states during a transaction. In order

to meet the tA parameter, a minimum frequency for SYSCLK5 is specified for each PIO as follows:

•

PIO mode 0, MIN frequency = 15 MHz

•

PIO mode 1, MIN frequency = 22 MHz

•

PIO mode 2, MIN frequency = 31 MHz

•

PIO mode 3, MIN frequency = 45 MHz

•

PIO mode 4, MIN frequency = 57 MHz

146

Peripheral and Electrical Specifications

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