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SPEAR600 Datasheet(PDF) 78 Page - STMicroelectronics |
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SPEAR600 Datasheet(HTML) 78 Page - STMicroelectronics |
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78 / 97 page ![]() Timing characteristics SPEAr600 78/97 Doc ID 16259 Rev 3 Note: Values in Table 48 are referred to the common internal source clock which has a period of THCLK = 6 ns. 6.5.2 16-bit NAND Flash configuration Figure 28. Output pads for 16-bit NAND Flash configuration Figure 29. Input pads for 16-bit NAND Flash configuration Figure 30. Output command signal waveforms 16-bit NAND Flash configuration Q Q SET CLR D Q Q SET CLR D HCLK NFALE NFCLE NFIO_0..7 NFCE NFWE NFRE NFRWPRT ... ... ... CLPOWER CLLP CLLE CLFP CLCP CLAC CLD_23..22 (NFIO_8..15) Q Q SET CLR D Q Q SET CLR D HCLK NFIO_0..7 NFRB ... ... CLPOWER CLLP CLLE CLFP CLCP CLAC CLD_23..22 (NFIO_8..15) NFCLE NFCE NFWE NFIO Command TCLE TWE TIO |
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