SPEAR600 datasheet(21/97 Pages) STMICROELECTRONICS

21 / 97 page

SPEAr600

Architecture overview

Doc ID 16259 Rev 3

21/97

Each PLL uses an oscillator input of 30 MHz to generate a clock signal at a frequency

corresponding to the highest of the group. This is the reference signal used by the multi

clock generator block to obtain all the other required clocks for the group. Its main feature is

electromagnetic interference reduction capability.

The user can set up the PLL in order to modulate the VCO with a triangular wave. The

resulting signal has a spectrum (and power) spread over a small programmable range of

frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic

emissions. This method replaces all the other traditional methods of EMI reduction, such as

filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal

shielding and so on. This gives the customer appreciable cost savings.

In sleep mode the SPEAr600 runs with the PLL disabled so the available frequency is 30

MHz or a sub-multiple (/2, /4, /16 and /32) or 32 KHz.

PLL3 is used to generate the USB controller clocks and it is not configured through

registers.

2.20

Vectored interrupt controller (VIC)

Each ARM Subsystem of SPEAr600 offers Vectored Interrupted Controller (VIC) blocks,

providing a software interface to the interrupt system.

Acting as an interrupt controller, the VIC determines the source that is requesting service

and where its interrupt service routine (ISR) is loaded, doing that in hardware.

In particular, the VIC supplies the starting address, or vector address, of the ISR

corresponding to the highest priority requesting interrupt source.

Main features of the VIC are listed below:

●

Support for 32 standard interrupt sources (a total of 64 lines are available for each CPU

from its two daisy-chained VICs).

●

Generation of both Fast Interrupt request (FIQ) and Interrupt Request (IRQ. IRQ is

used for general interrupts, whereas FIQ is intended for fast, low-latency interrupt

handling.

●

Support for 16 vectored interrupts (IRQ only);

●

Hardware interrupt priority

–

FIQ interrupt has the highest priority

–

followed by vectored IRQ interrupts, from vector 0 to vector 15

–

then non-vectored IRQ interrupts with the lowest priority

●

Interrupt masking/ interrupts request status

●

Software interrupt generation

2.21

General purpose timers

SPEAr600 provides five general purpose timers (GPTs) acting as APB slaves.

Each GPT consists of 2 channels, each one made up of a programmable 16-bit counter and

a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock

division by 1 up to 256, and different input frequencies can be chosen through SPEAr600

configuration registers (frequencies up to 83 MHz can be synthesized).

SPEAR600 Datasheet(PDF) 21 Page - STMicroelectronics

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