SPEAR600 datasheet(17/97 Pages) STMICROELECTRONICS

17 / 97 page

SPEAr600

Architecture overview

Doc ID 16259 Rev 3

17/97

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Native DMA with single-channel Transmit and Receive engines, providing 32/64/128-bit

data transfers

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DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining

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A set of CSRs to control DMA operation

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An AHB slave acting as programming interface to access all CSRs, for both DMA and

GMAC core subsystems

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An AHB master for data transfer to system memory

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32-bit AHB master bus width, supporting 32-bit wide data transactions

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Supports both big-endian and little-endian byte ordering

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Power Management Module (PMT) with Remote Wake-up and Magic Packet frame

processing options

2.11

USB2 host controller

SPEAr600 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks:

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EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)

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OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)

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Local 2-Kbyte FIFO

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Local DMA

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Integrated USB2 transceiver (PHY)

Both hosts can manage an external power switch, providing a control line to enable or

disable the power, and an input line to sense any over-current condition detected by the

external switch.

Both host controllers can perform high speed transfer simultaneously.

2.12

USB2 device controller

Main features:

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Supports 480 Mbps high-speed mode (HS) for USB 2.0, as well as 12 Mbps full-speed

(FS) and the low-speed (LS modes) for USB 1.1

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Supports 16 physical endpoints, which can be assigned to different interfaces and

configurations to implement logical endpoints

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Integrated USB transceiver (PHY)

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Local 4 Kbyte FIFO shared by all endpoints

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DMA mode and slave-only mode are supported

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In DMA mode, the UDC supports descriptor-based memory structures in application

memory

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In both modes, an AHB slave is provided by UDC-AHB, acting as programming

interface to access to memory-mapped control and status registers (CSRs)

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An AHB master for data transfer to system memory is provided, supporting 8, 16, and

32-bit wide data transactions on the AHB bus

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A USB plug detect (UPD) which detects the connection of a cable.

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