W39V040FAQ datasheet(9/36 Pages) WINBOND

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W39V040FA

Publication Release Date: December 19, 2002

- 9 -

Revision A2

FWH Cycle Definition

FIELD

NO. OF

CLOCKS

DESCRIPTION

START

"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH

Memory Write cycle. 0000b" appears on FWH bus to indicate the initial

IDSEL

This one clock field indicates which FWH component is being selected.

MSIZE

Memory Size. There is always show “0000b” for single byte access.

TAR

Turned Around Time

ADDR

Address Phase for Memory Cycle. FWH supports the 28 bits address

protocol. The addresses transfer most significant nibble first and least

significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and

Address[3:0] on FWH[3:0] last.)

SYNC

Synchronous to add wait state. "0000b" means Ready, "0101b" means

Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"

means error, and other values are reserved.

DATA

Data Phase for Memory Cycle. The data transfer least significant nibble

first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then

DQ[7:4] on FWH[3:0] last.)

W39V040FAQ Datasheet(PDF) 9 Page - Winbond