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W39V040FAQ Datasheet(PDF) 24 Page - Winbond |
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W39V040FAQ Datasheet(HTML) 24 Page - Winbond |
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24 / 36 page  W39V040FA - 24 - 11. TIMING WAVEFORMS FOR FWH INTERFACE MODE Read Cycle Timing Diagram TCYC FWH4 #RESET FWH[3:0] Start FWH Read IDSEL CLK 1 Clock 2 Clocks A[15:12] Address Sync TAR 1111b Tri-State 0000b TKQ THD TSU A[11:8] A[7:4] 0000 b] Data out 2 Clocks D[7:4] Data D[3:0] Next Start 1 Clock 0000b THD TSU Load Address in 7 Clocks A[3:0] M Size XXXXb XA[22]XXb XXA[18:16] 1 Clock 1 Clock 0000b 1101b Note: When A22 = high, the host will read the BIOS code from the FWH d While A22 = low, the host will read the GPI (Add = FFBC0100 Product ID (Add = FFBC0000/FFBC0001) from the FWH dev 1111b Tri-State 2 Clocks TAR Write Cycle Timing Diagram TCYC FWH4 #RESET FWH[3:0] Start FWH Write IDSEL CLK Next Start 1 Clock 1 Clock A[15:12] Load Data in 2 Clocks D[7:4] Address Sync 2 Clocks TAR Data 1111b Tri-State 0000b THD TSU A[11:8] A[7:4] 0000b D[3:0] 0000b Load Address in 7 Clocks A[3:0] M Size XXXXb XXXXb XXA[18:16]b 1 Clock 1 Clock 0000b 1110b 2 Clocks TAR 1111b Tri-State |
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