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W39V040FAQ Datasheet(PDF) 23 Page - Winbond |
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W39V040FAQ Datasheet(HTML) 23 Page - Winbond |
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23 / 36 page ![]() W39V040FA Publication Release Date: December 19, 2002 - 23 - Revision A2 10. FWH INTERFACE MODE AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0.6 VDD to 0.2 VDD Input Rise/Fall Slew Rate 1 V/nS Input/Output Timing Level 0.4VDD / 0.4VDD Output Load 1 TTL Gate and CL = 10 pF Read/Write Cycle Timing Parameters (VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C) W39V040FA PARAMETER SYMBOL MIN. MAX. UNIT Clock Cycle Time TCYC 30 - nS Input Set Up Time TSU 7 - nS Input Hold Time THD 0 - nS Clock to Data Valid TKQ 2 11 nS Note: Minimum and Maximum time has different loads. Please refer to PCI specification. Reset Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT VDD stable to Reset Active TPRST 1 - - mS Clock Stable to Reset Active TKRST 100 - - µS Reset Pulse Width TRSTP 100 - - nS Reset Active to Output Float TRSTF - - 50 nS Reset Inactive to Input Active TRST 10 - - µS Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition. |
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