S29AS016J datasheet(53/59 Pages) CYPRESS

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Document Number: 002-01122 Rev.*L

Page 53 of 59

S29AS016J

19. Erase and Programming Performance

Notes

1. Typical program and erase times assume the following conditions: 25°C, VCC = 1.8 V, 100,000 cycles, checkerboard data pattern.

2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program

times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 32 for further information on

command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

20. Package Pin Capacitance

Notes

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.5

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

19.5

Byte Programming Time

µs

Excludes system level

overhead (Note 5)

Word Programming Time

150

µs

Chip Programming Time

(Note 3)

Byte Mode

160

Word Mode

120

Parameter Symbol

Parameter Description

Test Setup

Package

Typ

Max

Unit

CIN

Input Capacitance

VIN = 0

TSOP

4.0

6.0

BGA

4.2

5.0

COUT

Output Capacitance

VOUT = 0

TSOP

4.5

5.5

BGA

5.4

6.5

CIN2

Control Pin Capacitance

VIN = 0

TSOP

6.5

BGA

3.9

4.7

CIN3

WP# Pin Capacitance

VIN = 0

TSOP

8.5

10.0

BGA

8.5

10.0

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