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56F8167 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc |
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56F8167 Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 184 page ![]() Signal Pins 56F8367 Technical Data, Rev. 7.0 Freescale Semiconductor 23 Preliminary D0 (GPIOF9) 70 P10 Input/ Output Input/ Output In reset, output is disabled, pull-up is enabled Data Bus — D0 - D6 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), D0–D6 are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. Port F GPIO — These seven GPIO pins can be individually programmed as input or output pins. After reset, these pins default to the EMI Data Bus function. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF9, clear bit 9 in the GPIOF_PUR register. D1 (GPIOF10) 71 N10 D2 (GPIOF11) 83 P14 D3 (GPIOF12) 86 L13 D4 (GPIOF13) 88 L14 D5 (GPIOF14) 89 L12 D6 (GPIOF15) 90 L11 Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type State During Reset Signal Description |
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