56F8167 datasheet(24/184 Pages) FREESCALE

24 / 184 page

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

(GPIOF0)

Input/

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Data Bus — D7 - D15 specify part of the data for external

program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus control

inactive.

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

Port F GPIO — These nine GPIO pins can be individually

programmed as input or output pins.

At reset, these pins default to Data Bus functionality.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOF_PUR register.

Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.

(GPIOF1)

(GPIOF2)

D10

(GPIOF3)

D11

(GPIOF4)

149

D12

(GPIOF5)

150

D13

(GPIOF6)

151

D14

(GPIOF7)

152

D15

(GPIOF8)

153

Output

In reset,

output is

disabled,

pull-up is

enabled

Read Enable — RD is asserted during external memory read

cycles. When RD is asserted low, pins D0 - D15 become inputs

and an external device is enabled onto the data bus. When RD is

deasserted high, the external data is latched inside the device.

When RD is asserted, it qualifies the A0 - A23, PS, DS, and CSn

pins. RD can be connected directly to the OE pin of a static RAM

or ROM.

Depending upon the state of the DRV bit in the EMI bus control

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

To deactivate the internal pull-up resistor, set the CTRL bit in the

SIM_PUDR register.

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

56F8167 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

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