56F8167 datasheet(5/184 Pages) FREESCALE

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56F8367/56F8167 Features

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Part 1 Overview

1.1 56F8367/56F8167 Features

1.1.1

Core

•

Efficient 16-bit 56800E family controller engine with dual Harvard architecture

•

Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

•

Single-cycle 16

× 16-bit parallel Multiplier-Accumulator (MAC)

•

Four 36-bit accumulators, including extension bits

•

Arithmetic and logic multi-bit shifter

•

Parallel instruction set with unique DSP addressing modes

•

Hardware DO and REP loops

•

Three internal address buses and one external address bus

•

Four internal data buses and one external data bus

•

Instruction set supports both DSP and controller functions

•

Controller-style addressing modes and instructions for compact code

•

Efficient C compiler and local variable support

•

Software subroutine and interrupt stack with depth limited only by memory

•

JTAG/EOnCE debug programming interface

1.1.2

Differences Between Devices

Table 1-1 outlines the key differences between the 56F8367 and 56F8167 devices.

Table 1-1 Device Differences

Feature

56F8367

56F8167

Guaranteed Speed

60MHz/60 MIPS

40MHZ/40MIPS

Program RAM

4KB

Not Available

Data Flash

32KB

Not Available

PWM

2 x 6

1 x 6

CAN

Not Available

Quad Timer

Quadrature Decoder

2 x 4

1 x 4

Temperature Sensor

Not Available

Dedicated GPIO

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56F8167 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc

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