56F8167 datasheet(15/184 Pages) FREESCALE

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Introduction

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8367 and 56F8167 are organized into functional groups, as detailed

in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals

present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins in Package

56F8367

56F8167

Power (VDD or VDDA)9

Power Option Control

Ground (VSS or VSSA)7

Supply Capacitors1 & VPP

1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs

PLL and Clock

Address Bus

Data Bus

Bus Control

Interrupt and Program Control

Pulse Width Modulator (PWM) Ports

Serial Peripheral Interface (SPI) Port 0

Serial Peripheral Interface (SPI) Port 1

—

Quadrature Decoder Port 02

2. Alternately, can function as Quad Timer pins

Quadrature Decoder Port 13

3. Pins in this section can function as Quad Timer, SPI #1, or GPIO

4—

Serial Communications Interface (SCI) Ports2

CAN Ports

—

Analog to Digital Converter (ADC) Ports

Timer Module Ports

JTAG/Enhanced On-Chip Emulation (EOnCE)

Temperature Sense

—

Dedicated GPIO

—

56F8167 Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

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