56F8167 datasheet(132/184 Pages) FREESCALE

132 / 184 page

56F8367 Technical Data, Rev. 7.0

132

Freescale Semiconductor

Preliminary

EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM

input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] = 1. Using the

following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of

181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.

Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock

divider value must be shifted into the corresponding 7-bit data register. After the data register has been

updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout

sequence to commence. The controller must remain in this state until the erase sequence has completed.

For details, see the JTAG Section in the 56F8300 Peripheral User Manual.

Note:

Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller

(by asserting TRST) and the

device (by asserting external chip reset) to return to normal unsecured

operation.

7.2.4

Product Analysis

The recommended method of unsecuring a programmed device for product analysis of field failures is via

the backdoor key access. The customer would need to supply Technical Support with the backdoor key

and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows

backdoor key access must be set.

An alternative method for performing analysis on a secured microcontroller would be to mass-erase and

reprogram the Flash with the original code, but modify the security bytes.

To insure that a customer does not inadvertently lock himself out of the device during programming, it is

recommended that he program the backdoor access key first, his application code second, and the security

bytes within the FM configuration field last.

Part 8 General Purpose Input/Output (GPIO)

8.1 Introduction

This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User

Manual and contains only chip-specific information. This information supercedes the generic information

in the 56F8300 Peripheral User Manual.

8.2 Memory Maps

The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based

on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and

GPIOx_PER registers will change from port to port. Table 8-3 defines the actual reset values of these

registers.

SYS_CLK

(2)(8)

)

(

(DIV + 1)

150[kHz]

200[kHz]

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