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DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

39 of 113

This feature becomes active when VDD_PWR falls below VDDPWR_IIN_DWN, which is

programmable between 4.2 V and 4.9 V by bit VDD_PWR_DPM (register 0x0028:[2:0]). The DPM

feature can be disabled by setting bit VDD_PWR_DPM_DIS (register 0x0028 [4]) = 0x1. However,

when DPM is disabled, the USB power source may be pulled down, triggering Sleep mode or input

UVLO.

The event bit ISR_VDD_PWR_DPM (register 0x0003 [3]) is set to 0x1 and the SYS_FLT pin toggles

whenever the DA9072 is in this current-limited mode. In Charging mode, termination is ignored to

allow the battery to be charged with any remaining current.

4.5.5

Dynamic Power Path Mode

Dynamic Power Path mode (DPPM) manages the situation in which the total charging and system

current exceeds the VDD_PWR current limit. When the input current is clamped, VDD_SYS drops until it

reaches VDD_SYS_THR_DPPM (DPPM threshold). In DPPM, charging current is reduced to service the

system current at VDD_SYS. DPPM is only active during charging and toggles SYS_FLT and set an

interrupt bit ISR_VBAT_DPPM (register 0x0004 [1]) = 0x1.

If VDD_SYS drops further due to increasing load, the DA9072 eventually enters Battery Supplement

mode.

4.5.6

Battery Supplement Mode

The DA9072 enters Battery Supplement mode when VDD_SYS falls below VBAT. Battery Supplement

mode occurs in USB powered operation, regardless of whether the battery is charging or not. Similar

to DPPM mode, the total current at VDD_SYS exceeds the VDD_PWR current limit, causing

VDD_SYS to drop until it reaches the VBAT voltage. In this mode, the battery supplies current to

VDD_SYS, thus supplementing the input current to supply the system demands. In Battery

Supplement mode, the discharge current from the battery is limited by the over-discharge protection.

Battery Supplement mode toggles the SYS_FLT pin and sets an event bit ISR_BAT_SPPL (register

0x0005 [1]) = 0x1. The device exits Battery Supplement mode when the system load is reduced and

VDD_SYS rises above VBAT.

4.5.7

Input Over-Voltage Protection

The DA9072 protects itself (and downstream connections to VDD_SYS) against input over-voltage

conditions by disconnecting VDD_PWR from the power path. Over-voltage protection (OVP) kicks in

immediately when VDD_PWR exceeds the OVP threshold. Over-voltage events are common at USB

plug-in due to the inductance of the long cable, where the transient overshoot may exceed 10 V

depending on cable length, quality, and input capacitance. The VDD_PWR input is capable of

withstanding up to 20 V and remains in OVP until the voltage returns to nominal levels. During OVP,

VDD_PWR is disconnected from the power path and DA9072 is in normal battery powered operation.

When an over-voltage occurs, the event bit ISR_VDD_PWR_OVP (reg 0x0003 [0]) = 0x1 and SYS-

FLT toggles.

4.5.8

VDD_PWR Input Supply Impedance

The DA9072 charging path is typically supplied by a 5 V USB source. USB cable resistance can

range from hundreds of milliohms to ohms. At higher charging currents, this parasitic input

impedance may cause VDD_PWR to drop from 5 V into the DPM range.

High USB cable resistance can lead to oscillations in DPM or Sleep mode. As VDD_PWR drops, the

DA9072 attempts to reduce current demand, which in turn causes VDD_PWR and current draw to

increase again. Follow the guidelines in Figure 24

to ensure that the DA9072’s internal hysteresis is

be sufficient to overcome these effects. The worst case is at highest battery voltage, the VBAT_CHG

regulation point.

It is recommended to always enable the DPM function, with the threshold set at least 0.4 V above the

VBAT_CHG voltage. Referring to Figure 24, with a DPM setting of 4.5 V and VBAT = 4.2 V, the

system has the potential to oscillate at any current greater than 75 mA. Note that this would only

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