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DA9072 Datasheet(PDF) 41 Page - Dialog Semiconductor |
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DA9072 Datasheet(HTML) 41 Page - Dialog Semiconductor |
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41 / 113 page ![]() DA9072 Ultra-Low Quiescent Current PMIC Datasheet Revision 3.0 14-Jun-2021 CFR0011-120-00 41 of 113 © 2021 Dialog Semiconductor Two timers apply to power cycling: the wait timer and the period timer. The wait time allows the host to take action before power is shut down and can be set between 0 s and 2 s. The period timer controls how long the outputs are powered down before restart and can be set between 5 s and 20 s. Both timers are programmable, the wait timer by PWR_CYC_WAIT_PER (register 0x0012 [7:6]) and the period timer by PWR_CYC_PER (register 0x0012 [5:4]). The power cycle timing using the RIN_N pushbutton is shown in Figure 25. The RESET time is set by bits RIN_N_PER_RST (register 0x0010 [7:6]). The RIN_N push button timer can be used for power cycling only when VDD_PWR is present. RIN_N SYS_FLT ROUT_N tINTR tRST_D tWAKE2 tWAKE1 (don t care) LDOx tINTR tINTR tRESET tWAIT tPERIOD Buck Figure 25: Power Cycle by Push Button Timer Alternately, the VDD_PWR plug can be used to initiate a power cycle as shown in Figure 26. VDD_PWR must go low and high three times within 8 s. After the 8 s period, the power cycle begins. VDD_PWR (case 1) SYS_FLT ROUT_N tRST_D LDOx tINTR < 8 sec tPERIOD UVLO tWAIT UVLO VDD_PWR (case 2) >150ms >150ms Buck Figure 26: Power Cycle by VDD_PWR Insertion The force power cycle bit PWR_CYC_FRC (register 0x0012 [2]) follows the same power cycle period and behavior but does not impose any wait time; power cycle shutdown occurs immediately. 4.6.2 Fault Triggered Power Cycle The DA9072 also initiates a power cycle in response to various fault conditions, listed in Table 29. Those not listed as always on trigger a power cycle only if that option is enabled. Fault triggered power cycles are intended to protect the system from a potentially damaging condition. The behavior is different to a user-initiated power cycle. When a fault triggered power cycle occurs, the wait time is skipped and all outputs are shut down immediately. When the power cycle period ends, the initial OTP register values are re-loaded at restart, including any outputs that are enabled by default. |
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