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DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

40 of 113

occur if VDD_PWR drops into the DPM or sleep region. For this example, a DPM setting of 4.6 V or

4.7 V is recommended for currents above 75 mA. Note

Figure 24: VDD_PWR DPM Setting Recommendations (Based on Typical USB Cable

Impedance)

4.6

Power Cycling

The power cycle function disables all outputs (buck, and LDOs) for a programmable time period and

then restarts. Power cycling can be initiated by a fault condition, RIN_N pushbutton, VDD_PWR

insertion, or I command. The primary purpose of power cycling is to clear a serious fault condition

such as IC over-temperature (OVT) or to reset the host.

4.6.1

Requested Power Cycle

The power cycle settings are configured at by SYS_PWR_CYC_0 (register 0x0012). There are three

methods to request a power cycle: by register write to PWR_CYC_FRC, by holding the RIN_N push

button low for the reset period, or by inserting and removing VDD_PWR. The setting options are

summarized in Table 28.

Table 28: Power Cycle Trigger Settings

PWR_CYC_EN

0x0012 [0]

PWR_CYC_MODE

0x0012 [1]

RIN_N RESET

Wake-Up Timer

VDD_PWR

Insertion /

Removal

PWR_CYC_FRC

0x0012 [2]

0x0

N/A

Disable

0x1

0x0

Disable

Enable

0x1

Enable

Disable

Enable

After any of these three host or user-initiated power cycles the buck and LDO outputs are disabled.

When auto-restart occurs, only the buck restarts. All register settings are preserved at restart with the

exception of the output enable registers. There is also a READ clear event bit STS_PWR_CYC

(register 0x0002 [1]) to indicate that a power cycle has occurred.

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