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DA9072 Datasheet(PDF) 10 Page - Dialog Semiconductor |
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DA9072 Datasheet(HTML) 10 Page - Dialog Semiconductor |
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10 / 113 page  DA9072 Ultra-Low Quiescent Current PMIC Datasheet Revision 3.0 14-Jun-2021 CFR0011-120-00 10 of 113 © 2021 Dialog Semiconductor Pin # Pin Name Type (Table 2) Description B1, B2 VBAT POWER Battery connection. Connect to the positive terminal of the battery. Bypass to ground with a minimum 1 µF ceramic capacitor. B3 IMON AO Battery discharge current monitor output. B4 TEMP_SNS AI Battery pack NTC monitor. Connect to a resistive network and thermistor. B5 SYS_FLT DOD Open drain status output. Connect to VDDIO through a 1 kΩ to 100 kΩ pull-up resistor. B6 SDA DIO I2C interface data. Connect SDA to VDDIO through a 2 k Ω to10 k Ω pull-up resistor. B7 FB_BUCK AI Buck output voltage feedback connection. C1 VBAT_SNS AI Battery voltage sense connection. Connect to the positive battery terminal. C2 ITER_CHG AI Termination current setting pin. Connect a resistor between ITER_CHG and ground to set the pre-charge and termination currents (ITER). Alternatively, short this pin to ground to allow ITER to be programmed by register setting. C3 ILIM_CHG AI Fast-charge current setting pin. Connect a resistor between ILIM_CHG and ground to set the fast-charge current (ICHG). Alternatively, short this pin to ground to allow ICHG to be programmed by register setting. C4 WD DI Watchdog input. Toggle WD within the watchdog time-out period to avoid power reset. C5 RIN_N DI Manual reset input pin. RIN_N is internally pulled high. Pulling this pin low wakes up the device from Ship mode or performs a reset. C6 SCL DI I2C interface clock. Connect SCL to VDDIO through a 2 k Ω to10 kΩ pull-up resistor. C7 AGND GND Quiet ground connection. Connect to a quiet ground area. D2 ILIM_PWR AI Input current limit setting pin. Connect a resistor between ILIM_PWR and ground to set the VDD_PWR current limit (ILIM). Alternatively, short this pin to ground to allow ILIM to be programmed by register. D4 VBAT_DIV AO Battery voltage divider, positive output. D5 MODE DI Mode control input pin. MODE is internally pulled low. If VDD_PWR is powered, driving MODE high disables charging. If VDD_PWR is unpowered, driving MODE low enables Hi-Z mode. D6 ROUT_N DOD Reset output pin. Connect this open-drain output to VDDIO through a 1 k Ω to 100 kΩ pull-up resistor. D7 PWR_FLT DOD Power status indicator output. Connect this open-drain output to VDDIO through a 1 kΩ to 100 kΩ pull-up resistor. PWR_FLT pulls low when VDD_PWR is plugged into a valid power source. E2 VTEMP AO Switched VDD_SYS supply for battery temp sense resistor divider. E3 VDDIO POWER IO voltage. E4 GND_DIV AO Battery voltage divider, ground reference. E5 VDD_LDO2 POWER Input to Load Switch / LDO2. Bypass to ground with a minimum 1 µF ceramic capacitor. |
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