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DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

52 of 113

VDD_SYS, the buck output, or another suitable source. If using the buck output, confirm that the

buck provides sufficient headroom and current capability.

In LDO mode, LDO0 can be programmed between 0.8 V and 3.15 V in 25 mV or 50 mV steps. LDO1

and LDO2 can be set between 0.8 V and 3.3 V in 50 mV or 75 mV steps. To ensure good regulation

and full load capability, 200 mV of headroom is recommended at VDD_LDO<n>, with load capability

decreasing with lower headroom. With sufficient headroom the LDOs are current limited at a

minimum of 215 mA. LDO0 is designed to operate with lower headroom.

To achieve the best performance from the LDOs, it is recommended that the input bypass cap is

placed as close as possible to the LDO input pins (VDD_LDO<n>). A 1 µF input capacitor is typically

sufficient for each LDO, provided that there is at least that much capacitance at the VDD_SYS or

BUCK output.

Each LDO is enabled and output voltage set by registers VOUT_LS_LDO<n> (0x0032 through

0x0034). The LDOs can be configured as load switches by bits SEL_LDSW_<n> (register 0x0035

[2:0]). There is an approximately 20 ms delay between the I2C enable command and LDO startup.

When the LDOs are operating as load switches, there are two modes of operation: Current Limit

Enabled mode and Full-On mode. Full-On mode disables the load switch current limit, while

providing a much lower on-resistance.

In Current Limit mode, current limit is active with the same limit as the LDO mode limit. Each load

switch can operate over a wider range compared to LDO mode, with a minimum input voltage of

0.8 V.

In either mode, the load switch current capability is reduced at lower input voltages. At the minimum

input voltage, expect a maximum load-switch capability of 1 mA.

4.11 Thermal Protection

DA9072 is protected from internal overheating by the over-temperature shutdown function. When the

junction temperature reaches TSHDN , the device initiates a power cycle and the safety timer is reset.

When the power cycle ends, VDD_SYS recovers for several milliseconds. After this period, if the

junction temperature is still above TSHDN, a power cycle is initiated again. In this way, the DA9072

continually attempts to restart with an active duty cycle of less than 1 %, sufficient to allow the IC to

cool down. When the junction temperature has dropped below TSHDN

– THYS, power cycling stops.

When an over-temperature fault occurs, SYS_FLT toggles and the ISR_OVT bit (register 0x0007 [3])

is set to 1.

To avoid tripping thermal shutdown, limit power dissipation to no more than:

�� <

118℃ − ��

��_��

Where TA is the ambient temperature, RTH_JA is the combined thermal resistance of the package and

PCB. Typical values for RTH_JA vary with PCB size, layer count, airflow, and other factors. A typical

value of 40 ºC/W is a good starting point. PDISS can be estimated as:

�� = �� + ��0 +��1 + ��2 + ��

Where:

● PLDO0 = (VDD_LDO0 – VLDO0) * ILDO0

● PLDO1 = (VDD_LDO1 – VLDO1) * ILDO1

● PLDO2 = (VDD_LDO2 – VLDO2) * ILDO2

● PCHG = (VDD_PWR – VBAT) * ICHG

● PBUCK = VO_BUCK * IOUT_BUCK * (1/η 1) – DCR * IOUT_BUCK

○ where η is the efficiency of the buck converter and DCR is the inductor’s DC resistance.

4.12 PCB Layout Guidelines

To ensure proper operation and maximize optimal thermal performance following these guidelines.

DA9072 Datasheet(PDF) 52 Page - Dialog Semiconductor

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