6

Operating modes

6.1

Turn-on

When the input voltage is applied, the enable/fault pin goes up to the high state, enabling the internal control

circuitry.

After an initial delay time of typically 350 µs, the output voltage is supplied with a slope defined by the internal

dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the total time, from the enable signal going high

to the output voltage reaching the nominal value, is around 1 ms (refer to Figure 5. Delay time and VOUT ramp-up

time).

6.2

Normal operating conditions

The STEF12E E-Fuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage

shown on its input, with a small voltage fall due to the N-channel MOSFET RDS(on).

6.3

Output voltage clamp

This internal protection circuit clamps the output voltage to a maximum safe value, typically 15 V, if the input

voltage exceeds this threshold.

6.4

Current limiting

When an overload event occurs, the current limiting circuit reduces the conductivity of the power MOSFET,

in order to clamp the output current at the value selected externally by the limiting resistor RLimit (see

Figure 3. Application circuit).

6.5

Thermal shutdown

If the device temperature exceeds the thermal latch threshold, typically 165 °C, the thermal shutdown circuitry

turns the power MOSFET off, thus disconnecting the load. The EN/fault pin of the device is automatically set to an

intermediate voltage, in order to signal the overtemperature event. In this condition the E-Fuse can be reset either

by cycling the supply voltage or by pulling down the EN pin below the VIL threshold and then releasing it.

6.6

R-Lim calculation

As shown in Figure 3. Application circuit, the device uses an internal N-channel SenseFET with a fixed ratio, to

monitor the output current and limit it at the level set by the user.

To achieve the requested current limitation, the R-Lim value can be estimated by using the following theoretical

formula, together with the graph in Figure 13. Current limit vs. RLimit .

RLim= 95ISℎort

(1)

6.7

Cdv/dt calculation

Connecting a capacitor between the Cdv/dt pin and GND allows the modification of the output voltage ramp-up

time.

Given the desired time interval ∆t, during which the output voltage goes from zero to its maximum value, the

capacitance to be added to the Cdv/dt pin can be calculated using the following theoretical formula:

Cdvdt=3.92 × 10−8∆t−35.3 × 10−12

(2)

Where Cdv/dt is expressed in farads and the time in seconds.

The addition of an external Cdv/dt also influences the initial delay time, defined as the time between the enable

signal going high and the start of the VOUT slope (Figure 5. Delay time and VOUT ramp-up time).

The contribution of the external capacitor to this time interval can be estimated by using the following theoretical

formula:

delay time s =35 × 10−5+71 × 105 × Cdv/dt F

(3)

STEF12E

Operating modes

DS12800 - Rev 2

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