Preliminary Technical Data

AD5522

Rev. PrL | Page 33 of 45

DAC Addressing

For the FIN and Comparator (CPH & CPL) DACs, there are sets of x1, m and c registers for each current range and for the voltage range,

but only two sets for the Clamp function (CLL and CLH).

When calibrating the device, m and c registers allow volatile storage of offset and gain coefficients. Calculation of the corresponding DAC

x2 register only occurs when x1 data is loaded (no internal calculation occurs on m or c updates).

There is one Offset DAC per all four channels in the device, it is addressed through any PMU0-3 address. The Offset DAC only has an

input register associated with it; there are no m or c registers for this DAC. When writing to this DAC, set both Mode bits high to address

the DAC input register (x1).

This address table is also used for readback of a particular DAC address.

Table 21. DAC Register Addressing

Address bits A5 to A3 (DAC ADDRESS Register)

Register Set

000

001

010

011

100

101

110

111

MODE1

MODE0

0

1

RESERVED

1

0

RESERVED

000

±5µA I range

1

1

OFFSET DAC

FIN

RESERVED

RESERVED

CPL

CPH

RESERVED

RESERVED

001

±20µA I range

RESERVED

FIN

RESERVED

RESERVED

CPL

CPH

RESERVED

RESERVED

010

±200µA I range

RESERVED

FIN

RESERVED

RESERVED

CPL

CPH

RESERVED

RESERVED

011

±2mA I range

RESERVED

FIN

RESERVED

RESERVED

CPL

CPH

RESERVED

RESERVED

100

±external I range

RESERVED

FIN

CPL

CPH

RESERVED

RESERVED

101

Voltage range

RESERVED

FIN

CPL

CPH

RESERVED

RESERVED

110

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

A2 to A0

(REGISTER

ADDRESS)

111

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

loaded to the Clamp DAC.

loaded to the Clamp DAC.