AD5522JSVDZ datasheet(26/45 Pages) AD

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AD5522

Preliminary Technical Data

Rev. PrL | Page 26 of 45

Table 12. BUSY Pulse Width

Action

BUSY Pulse Width

(

μs max)

Loading data to PMU, System Control

0.15

Loading x1 to any 1 PMU DAC Channel

1.25

Loading x1 to any 2 PMU DAC Channels

1.75

Loading x1 to any 3 PMU DAC Channels

2.25

Loading x1 to any 4 PMU DAC Channels

2.75

BUSY Pulse Width = ((Number of channels +1) × 500ns) + 250ns

BUSY also goes low during power-on reset and when a falling

edge is detected on the RESET pin.

WRITE

1st

STAGE

2nd

STAGE

3rd

STAGE

~600ns

500ns

250ns

Calibration Engine Time

e.g. WRITE TO

3 FIN DAC REGISTERS

1st

STAGE

2nd

STAGE

3rd

STAGE

1st

STAGE

2nd

STAGE

3rd

STAGE

1st

STAGE

2nd

STAGE

3rd

STAGE

WRITE

Figure 17. Multiple writes to DAC x1 registers

Writing data to the System control register, PMU control

engine, thus speeding up configuration of the device on power

on.

As mentioned previously the value of the X2 register is

calculated each time the user writes new data to the

corresponding X1 register. The calculation is performed by a

three stage process. The first two stages take 500ns each and the

third stage takes 250ns. When the writes to one of the X1

registers is complete the calculation process begins. If the write

operation involves the update of a single DAC channel the user

is free to write to another register provided that the write

operation doesn’t finish until the first stage calculation is

complete, i.e. 500ns after the completion of the first write

operation.

~600ns

500ns

250ns

Calibration Engine Time

1st

STAGE

2nd

STAGE

3rd

STAGE

WRITE

1st

STAGE

2nd

STAGE

3rd

STAGE

WRITE

1st

STAGE

2nd

STAGE

3rd

STAGE

WRITE

Figure 18. Multiple Single Channel writes engaging calibration engine

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