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AD5522JSVDZ Datasheet(PDF) 35 Page - Analog Devices |
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AD5522JSVDZ Datasheet(HTML) 35 Page - Analog Devices |
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35 / 45 page ![]() Preliminary Technical Data AD5522 Rev. PrL | Page 35 of 45 READBACK OF SYSTEM CONTROL REGISTER The readback function is a 24 bit word, mode, address and System Control Register data bits as shown in the following table. Table 23. Readback System Control Register Data Bit Bit name Description 23 (MSB) MODE1 0 22 MODE0 0 SYSTEM CONTROL REGISTER SPECIFIC READBACK BITS 21 CL3 20 CL2 19 CL1 18 CL0 Readback the status of the individual Clamp Enable bits. A “0” means the clamp is disabled, while a “1” enabled. The clamp enable function is also available in the System Control Register. This dual functionality allows flexible enable or disabling of this function. When reading back information on the status of the clamp enable function, what was most recently written to the clamp register from either System Control register or PMU register will be available in the readback word. 17 CPOLH3 16 CPOLH2 15 CPOLH1 14 CPOLH0 Readback information on the Comparator Output Enable status. A “1” signifies the function is enabled, while a “0” disabled. A logic high indicates that the PMU comparator output is enabled, while if low, it’s disabled. The comparator output enable function is also available in the PMU Register. This dual functionality allows flexible enable or disabling of this function. When reading back information on the status of the comparator output enable function, what was most recently written to the comparator register from either System Control register or PMU register will be available in the readback word. 13 CPBIASEN This readback bit tells the status of the Comparator Enable function. A “1” in this bit position means the Comparator functions are enabled, while a “0” disabled. 12 DUTGND/CH DUTGND per channel enable. If this bit is set at “1”, DUTGND per channel is enabled, while if “0”, individual guard inputs are available per channel. 11 GUARD ALM 10 CLAMP ALM These bits give status on which of these alarm bits trigger the CGALM pin. 9 INT10K If this bit is set high, the internal 10k resistor is connected between FOH and MEASVH, and between DUTGND and AGND. If low, they are disconnected. 8 GUARD EN Readback status of the Guard amplifies. If high, Amplifiers are enabled. 7 GAIN1 6 GAIN0 Status of the selected MEASOUT Output Range. 5 TMP ENABLE 4 TMP1 3 TMP0 Information is available on the status of the setting for Thermal shutdown function. Refer to System control write register. 2 LATCHED This bit tells of the status of the open drain outputs. When high, the open drain alarm outputs are latched outputs, while if low, they are unlatched. 1 0 (LSB) Unused Readback bits Will be loaded with zeros. |
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