Preliminary Technical Data

AD5522

Rev. PrL | Page 27 of 45

REGISTER SELECTION

The serial word assignment consists of 29 bits. Bits 28 through

to 22 are common to all registers, whether writing to or reading

from the device. PMU3 to PMU0 data bits address each PMU

channel (or associated DAC register). When PMU3 to PMU0

are all zeros, the System Control Register is addressed. Mode

Bits MODE0 and MODE1 address the different sets of DAC

registers and the PMU register.

Readback Control, RD/WR

The R/W bit set high initiates a readback sequence of PMU,

Alarm, Comparator, System Control Register or DAC

information as determined by address bits.

PMU Address Bits, PMU3, PMU2, PMU1, PMU0

Bits PMU3 through PMU0 address each of the PMU channels

on chip. This allows individual control of each PMU channel or

any manner of combined addressing in addition to multi

channel programming. PMU bits also allow access to write

registers such as the System Control Register and the many

DAC registers, in addition to reading from all the registers.

Table 13. Mode Bits

B23

B22

WRITE FUNCTION

MODE1

MODE0

Action

0

0

System Control Register or PMU Register

0

1

DAC Gain (m) Register

1

0

DAC Offset (c) Register

1

1

DAC Input Data Register, (x1)

Table 14. Read and Write Functions of the AD5522

B28

B27

B26

B25

B24

B23

B22

B21 to B0

SELECTED REGISTER

RD/WR

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

DATA BITS

CH3

CH2

CH1

CH0

WRITE FUNCTIONS

0

0

0

0

0

0

0

DATA BITS

Write to System Control Register (

0

0

0

0

0

0

1

DATA BITS

RESERVED

0

0

0

0

0

1

0

DATA BITS

RESERVED

0

0

0

0

0

1

1

11 1111 1111 1111 1111 1111b

NOP (No Operation)

0

0

0

0

0

1

1

DATA BITS other than all 1’s

RESERVED

WRITE ADDRESSED DAC OR PMU REGISTER

0

0

0

0

1

×

×

×

CHO

0

0

0

1

0

×

×

CH1

×

0

0

0

1

1

×

×

CH1

CH0

0

0

1

0

0

×

CH2

×

×

0

-

-

-

-

-

-

-

-

0

1

0

0

0

CH3

×

×

×

0

-

-

-

-

-

-

-

-

0

1

1

1

0

CH3

CH2

CH1

×

0

1

1

1

1

Select DAC or PMU Registers.

See Table 13

DATA BITS

CH3

CH2

CH1

CH0

READ FUNCTIONS

1

0

0

0

0

0

0

All zeros

Read from System Control Register

1

0

0

0

0

0

1

All zeros

Read from Comparator Status Registers

1

0

0

0

0

1

0

X

Reserved

1

0

0

0

0

1

1

All zeros

Read from Alarm Status Register

READ ADDRESSED DAC or PMU REGISTER – Can only read one PMU or DAC register at one time.

1

0

0

0

1

×

×

×

CH0

1

0

0

1

0

×

×

CH1

×

1

0

1

0

0

×

CH2

×

×

1

1

0

0

0

PMU/.DAC REGISTER ADDRESS

SEE

Table 13

DAC ADDRESS SEE

Table 21

CH3

×

×

×

NOP (No Operation)

If a NOP (No Operation) command is loaded, no change is made to DAC or PMU registers. This code is useful when performing a read

back of a register within the device (via the SDO pin) where a change of DAC code or PMU function may not be required

Reserved Commands

Any bit combination that is not described in the Register address tables for the PMU, DAC and System Control Registers are Reserved

commands. These commands are unassigned commands; they are reserved for factory use. To ensure correct operation of the device, do

not used reserved commands.