SST55LD019M datasheet(21/59 Pages) SST

21 / 59 page

Advance Information

ATA Flash Disk Controller

SST55LD019M

S71312-01-000

12/06

10.1.2.9 Status & Alternate Status Registers (Read Only)

These registers return the ATA Flash Disk Controller status when read by the host. Reading the Status register does

clear a pending interrupt while reading the alternate Status register does not. The meaning of the status bits are

described as follows:

Symbol

Function

BUSY

The busy bit is set when the ATA Flash Disk Controller has access to the command

buffer and registers and the host is locked out from accessing the Command register and

buffer. No other bits in this register are valid when this bit is set to a 1.

RDY

RDY indicates whether the device is capable of performing ATA Flash Disk Controller

operations. This bit is cleared at power up and remains cleared until the ATA Flash Disk

Controller is ready to accept a command.

DWF

This bit, if set, indicates a write fault has occurred.

DSC

This bit is set when the ATA Flash Disk Controller is ready.

DRQ

The Data-Request bit is set when the ATA Flash Disk Controller requires that information

be transferred either to or from the host through the Data register.

CORR

This bit is set when a correctable data error has been encountered and the data has

been corrected. This condition does not terminate a multi-sector Read operation.

ERR

This bit is set when the previous command has ended in some type of error. The bits in

the Error register contain additional information describing the error. It is required that

the host retry any media access command (such as Read-Sector and Write-Sector) that

ends with an error condition.

10.1.2.10 Device Control Register (Write Only)

This register is used to control the ATA Flash Disk Controller interrupt request and to issue a software reset. This

Symbol

Function

SW Rst

This bit is set to 1 in order to force the ATA Flash Disk Controller to perform a software

Reset operation. The chip remains in reset until this bit is reset to ‘0.’

-IEn

0: The Interrupt Enable bit enables interrupts

1: Interrupts from the ATA Flash Disk Controller are disabled

This bit is set to 0 at Power-on and Reset.

Reset Value

BUSY

RDY

DWF

DSC

DRQ

CORR

ERR

1000 0000b

Reset Value

XXX

SW Rst

-IEn

0000 1000b

SST55LD019M Datasheet(PDF) 21 Page - Silicon Storage Technology, Inc

SST55LD019M Datasheet(HTML) 21 Page - Silicon Storage Technology, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL