SST55LD019M datasheet(6/59 Pages) SST

6 / 59 page

Advance Information

ATA Flash Disk Controller

SST55LD019M

S71312-01-000

12/06

1.0 GENERAL DESCRIPTION

The ATA Flash Disk Controller contains a microcontroller

and embedded flash file system integrated in TQFP and

TFBGA packages. Refer to Figure 2-1 for the ATA Flash

Disk Controller block diagram. The controller interfaces with

the host system allowing data to be written to and read

from the flash media.

1.1 Performance-optimized ATA Flash Disk

Controller

The heart of the flash drive is the ATA Flash Disk Controller

which translates standard ATA signals into flash media data

and control signals. The following components contribute to

the ATA Flash Disk Controller’s operation.

1.1.1 Microcontroller Unit (MCU)

The MCU translates ATA/IDE commands into data and

control signals required for flash media operation.

1.1.2 Internal Direct Memory Access (DMA)

The ATA Flash Disk Controller uses internal DMA allowing

instant data transfer from buffer to flash media. This imple-

mentation eliminates microcontroller overhead associated

with the traditional, firmware-based approach, thereby

increasing the data transfer rate.

1.1.3 Power Management Unit (PMU)

The power management unit controls the power consump-

tion of the ATA Flash Disk Controller. The PMU dramatically

reduces the power consumption of the ATA Flash Disk

Controller by putting the part of the circuitry that is not in

operation into sleep mode.

1.1.4 SRAM Buffer

A key contributor to the ATA Flash Disk Controller perfor-

mance is an SRAM buffer. The buffer optimizes the host’s

data transfer to and from the flash media.

1.1.5 Embedded Flash File System

The embedded flash file system is an integral part of the

ATA Flash Disk Controller. It contains MCU firmware that

performs the following tasks:

1. Translates host side signals into flash media

writes and reads.

2. Provides dynamic flash media wear leveling to

spread the flash writes across all unused memory

address space to increase the longevity of flash

media.

3. Keeps track of data file structures.

1.1.6 Error Correction Code (ECC)

The ATA Flash Disk Controller utilizes 72-bit Reed-

Solomon Error Detection Code (EDC) and Error Correc-

tion Code (ECC), which provides the following error

immunity for each 512-byte block of data:

1. Corrects up to three random 12-bit symbol errors.

2. Corrects single bursts up to 25 bits.

3. Detects single bursts up to 61 bits and double

bursts up to 15 bits.

4. Detects up to six random 12-bit symbol errors.

1.1.7 Serial Communication Interface (SCI)

The Serial Communication Interface (SCI) is designed to

enable the user to restart the self-initialization process and

to customize the drive identification information.

1.1.8 Multi-tasking Interface

The multi-tasking interface enables fast and sustained write

performance by allowing concurrent Read, Program, and

Erase operations to multiple flash media devices. This

interface optimizes the performance of Multi-Level Cell

(MLC) and high-density Single-Level Cell (SLC) flash

media.

SST55LD019M Datasheet(PDF) 6 Page - Silicon Storage Technology, Inc

SST55LD019M Datasheet(HTML) 6 Page - Silicon Storage Technology, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL