ADBMS2950BCCSZ datasheet(31/97 Pages) AD

31 / 97 page

Data Sheet

ADBMS2950B

Rev. 0 | Page 31 of 97

ADC MEASUREMENTS

The ADBMS2950B provides various ADC measurement paths

optimized for typical application requirements and are

described in the following chapters. All ADC inputs are

buffered. The Electrical Characteristics lists the available linear

input ranges. The OCxADC is monotonic over the absolute

maximum input voltage range of the IA, IB, and SA pins. The

IxADC is monotonic over the OCxADC input range. The

VxADC and VBxADC are also monotonic, including outside

the linear range of their input buffers. Their output does not

'roll over' or otherwise represents signals of the opposite

polarity.

There are various ways to check for the end of conversion

(EOC) of the various ADCs. In the simplest case, the host waits

for the maximum possible conversion time (typical time +10%)

before reading the result registers.

The conversion result registers can be cleared to the bitwise

inverse (all bits flipped) of their reset values using the clear

commands (CLRI, CLRA, CLRVX, and CLRO), which allows

the host to check for stuck faults of the result registers after

reset. The CLRA command that resets the accumulated result

registers must not be issued during continuous IxADC,

VBxADC operation as it might corrupt the ongoing or next

accumulation cycle. The CLRI, CLRVX, and CLRO commands

can be issued at any time.

Table 39 gives an overview of all ADCs and the related trigger

commands. The ADCs grouped in rows always convert

synchronously. Both IxADC, VBxADC channels convert

synchronously when commanded with ADIx, RD=1. The

OCxADC always operate continuously and the IxADC and

VBxADC depend on the OPT parameter of the ADIx

commands, as indicated in the Continuous column of Table 39.

The VxADC and AUX ADC do not operate continuously but

triggered on demand through ADV or ADX.

Table 39. Overview of ADCs and Related Trigger Commands

ADCs

Inputs

Trigger Command

Continuous

Description

OCxADC

I1A, I1B, I2A, I2B, I3A, I3B, VREF1-VREF2

WRCFGA (OCEN = 1)

Yes

Overcurrent ADCs.

I1ADC, VB1ADC

I1A, I1B, VBATx, SGND

ADI1

Yes (OPT)

Battery current and voltage ADCs channel 1.

I2ADC, VB2ADC

I2A, I2B, VBATx, SGND

ADI2

Yes (OPT)

Battery current and voltage ADCs channel 2.

V1ADC, V2ADC

V1 to V10, VREF2, VREF1P25, SGND

ADV

Voltage ADCs.

AUX ADC

See Table 48

ADX

Auxiliary ADC.

Battery Current Measurement

The ADBMS2950B features two low-offset measurement paths

to redundantly measure the voltage drop across a shunt resistor.

Both measurement paths contain 18-bits ADCs (I1ADC and

I2ADC) that allow the voltage developed over the shunt resistor

to be resolved down to 1 µV. Measurements are triggered

through the ADI1 and ADI2 commands with the typical

operation of I1ADC running in continuous mode and I2ADC

operating synchronously for redundancy or to execute various

diagnostic measurements. Both ADCs provide a measurement

result every 1 ms. If redundancy is required, the two ADCs run

in a perfectly synchronized lockstep to allow for result

comparison in the host controller. For the representation of the

measurement results, see the Memory Map description in the

respective registers.

If a new ADI1 or ADI2 command is received during

conversions, the ongoing conversions of the concerned ADCs

are stopped and new measurements are started, which allow the

re-synchronization of the ADBMS2950B to ADI battery stack

monitors. The corresponding result registers remain unchanged

upon reception of a new ADI1 or ADI2 and updated with the

new conversion results once the acquisition time (nominally

after 1 ms or ACCN times 1 ms) has elapsed.

Conversion Counters

For single-shot conversions, or in the case of the IxADCs, for

the first conversion after enabling the continuous mode, the

Poll commands (PLADC, PLI1, PLI2, PLV, and PLX) can be

used to determine if a conversion has completed. For

I1ADC/VB1ADC operating in continuous mode, the

Conversion Counter I1CNT that increments with each 1 ms

I1ADC/VB1ADC conversion allows to detect if new

conversions are available. For diagnostic purposes also the

I2ADC/VB2ADC operating in continuous mode provides the

Conversion Counter I2CNT that increments with each 1 ms

I2ADC/VB2ADC conversion. For the I1ADC/VB1ADC, the

I1PHA counter that increments four times per

I1ADC/VB1ADC conversion provides additional conversion

phase information. I1CNT and I1PHA can be treated as on 13-

bit counter I1CNTPHA[12:0] that increments four times for

every I1ADC/VB1ADC conversion.

Initialization Cycle

Upon receiving the first ADI1, ADI2, ADV, or ADX command

from within the REFUP state after power-up or SRST, the IC

enters the MEASURE state, and the IxADC initialization

process is started. The ADI1 or ADI2 commands must be sent

with OPT = 0b0000. Diagnostic measurements on IxADC and

VBxADC are not allowed during the IxADC initialization

phase.

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