ADBMS2950BCCSZ datasheet(52/97 Pages) AD

52 / 97 page

ADBMS2950B

Data Sheet

Rev. 0 | Page 52 of 97

Name

Type

Reset

Value

Description

Forces TMODE flag.

INJECC

ECC Diagnostic Enable.

Normal operation.

Inject bit error and trigger ECC logic to set SED1, SED2, MED1, and MED2.

INJOSC

Clock Monitor Diagnostic Enable.

Regular clock applied to clock monitor. No-clock detector in regular mode.

Faster clock applied to clock monitor. No-clock detector in regular mode.

Slower clock applied to clock monitor. No-clock detector checks for clock stuck high.

Regular clock applied to clock monitor. No-clock detector checks for clock stuck low.

INJMON

Supply Monitor and Deglitcher Diagnostic Enable.

Supply monitors operate normally. Deglitcher operates normally.

Supply monitors operate normally. Deglitcher mismatched forced to set OCMM flag.

Force undervoltage to trigger VDDUV, VREGUV, and VDIGUV checks.

Force overvoltage to trigger VREGOV, VDIGOV, VDE, and VDEL checks.

Note:

The host controller must keep log when setting the INJTS bit

for requesting the THSD bit to be asserted. After successfully

reading THSD, the INJTS bit must be cleared through

WRCFGA and the THSD bit must be cleared through

CLRFLAG. If a SRST is issued before clearing THSD, the FLAG

there is a thermal shutdown. Setting INJTS requests the THSD

to be asserted, but by itself does not trigger an internal reset.

Table 71. CFGB Register Map

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OC1TH[6:0]

OC2TH[6:0]

OC3TH[6:0]

OCDP

OCDGT[1:0]

OCBX

OCAX

OCMODE[1:0]

OC3GC

OC2GC

OC1GC

OCOD

GPIO4C

GPIO3C

GPIO2C

GPIO1C

GPIO2EOC

DIAGSEL[2:0]

Note: Any bits listed with 0 must be written with 0 during write

commands.

Table 72. CFGB Bit Description

Name

Type

Reset

Value

Description

OC1GC

OC1ADC Analog Input Gain Control.

OC1ADC Gain = 1 (OC1LSB = 5 mV).

OC1ADC Gain = 2 (OC1LSB = 2.5 mV).

OC2GC

OC2ADC Analog Input Gain Control.

OC2ADC Gain = 1 (OC2LSB = 5 mV).

OC2ADC Gain = 2 (OC2LSB = 2.5 mV).

OC3GC

OC3ADC Analog Input Gain Control.

OC3ADC Gain = 1 (OC3LSB = 5 mV).

OC3ADC Gain = 2 (OC3LSB = 2.5 mV).

OC1TH

0000000

OC1ADC Overcurrent Threshold. Magnitude of signed 7-bit result depends on gain setting.

0000000

OC1 output asserted irrespective of measured value.

0000001

OC1 output asserted when |OC1R| ≥ 1.

0000010

OC1 output asserted when |OC1R| ≥ 2.

0000011

OC1 output asserted when |OC1R| ≥ 3.

...

0111111

OC1 output asserted when |OC1R| ≥ 63.

1xxxxxx

OC1 output is deasserted. CLRO command clears the OC1R result register to 10000000.

OC2TH

0000000

OC2ADC Overcurrent Threshold. Magnitude of signed 7-bit result depends on gain setting.

0000000

OC2 output asserted irrespective of measured value.

0000001

OC2 output asserted when |OC2R| ≥ 1.

0000010

OC2 output asserted when |OC2R| ≥ 2.

0000011

OC2 output asserted when |OC2R| ≥ 3.

...

0111111

OC2 output asserted when |OC2R| ≥ 63.

1xxxxxx

OC2 output is deasserted. CLRO command clears the OC2R result register to 10000000.

OC3TH

0000000

OC3ADC Overcurrent Threshold. Magnitude of signed 7-bit result depends on gain setting.

ADBMS2950BCCSZ Datasheet(PDF) 52 Page - Analog Devices

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